WAFER LEVEL CHIP SIZE PACKAGE AND A MANUFACTURING METHOD THEREOF, CAPABLE OF ALLEVIATING THE STRESS WHICH IS GENERATED IN A SOLDER BALL FORMED ON A SEMICONDUCTOR CHIP

摘要

PURPOSE: A wafer level chip size package and a manufacturing method thereof are provided to alleviate the stress concentration applied to a solder ball due to the difference between coefficients of thermal expansion of a resin sealing unit and the solder ball by forming a dimorphism coating unit at the outer surface of the first solder ball which is formed on a semiconductor chip.;CONSTITUTION: A wafer level chip size package(100) includes a semiconductor chip, an insulating layer, a re-wring layer, the first solder ball, the dimorphism coating unit, and a resin sealing unit. On the semiconductor chip(101), a bonding pad(102) is formed. The insulating layer(104) is formed in the upper side of the semiconductor chip excepting for the bonding pad. One end of the re-wring layer(106) is connected to the bonding pad on the insulating layer and the other end has a connection pad(107). The first solder ball(110) is formed in the connection pad. The dimorphism coating unit(111) is formed in the outer surface of the first solder ball. The resin sealing unit(112) is formed so as to seal the re-wring layer, the insulating layer and the first solder ball.;COPYRIGHT KIPO 2010