首页> 外国专利> METHOD FOR FABRICATING AN ISOLATION LAYER OF A SEMICONDUCTOR DEVICE, CAPABLE OF PREVENTING DISLOCATION GENERATED IN AN ELEMENT ISOLATION LAYER

METHOD FOR FABRICATING AN ISOLATION LAYER OF A SEMICONDUCTOR DEVICE, CAPABLE OF PREVENTING DISLOCATION GENERATED IN AN ELEMENT ISOLATION LAYER

机译:制造半导体器件的隔离层的方法,其能够防止在元素隔离层中产生的错位

摘要

PURPOSE: A method for fabricating an isolation layer of a semiconductor device is provided to suppress inside of an element isolation layer by growing a silicon substrate in epitaxial after forming a trench and implanting impurity into an epitaxial layer.;CONSTITUTION: A trench is formed in a semiconductor substrate(100). An epitaxial silicon layer is formed inside the trench by epitaxially growing the semiconductor substrate . A photoresist pattern(120) is formed on the epitaxial silicon layer. An impurity is inserted into the epitaxial silicon layer. The trench is gap-filled with an oxide. An element isolation film is formed by planarizing the oxide.;COPYRIGHT KIPO 2010
机译:目的:提供一种制造半导体器件隔离层的方法,以通过在形成沟槽后在外延层中生长硅衬底并将杂质注入到外延层中来抑制元件隔离层的内部。半导体衬底(100)。通过外延生长半导体衬底,在沟槽内部形成外延硅层。在外延硅层上形成光致抗蚀剂图案(120)。杂质被插入到外延硅层中。沟槽被氧化物间隙填充。通过平坦化氧化物形成元件隔离膜。; COPYRIGHT KIPO 2010

著录项

  • 公开/公告号KR20100073418A

    专利类型

  • 公开/公告日2010-07-01

    原文格式PDF

  • 申请/专利权人 DONGBU HITEK CO. LTD.;

    申请/专利号KR20080132086

  • 发明设计人 MOON SANG TAE;

    申请日2008-12-23

  • 分类号H01L21/762;

  • 国家 KR

  • 入库时间 2022-08-21 18:32:21

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