首页> 外国专利> SILICIDE FORMING METHOD OF MOSFET OF A SEMICONDUCTOR DEVICE CAPABLE OF IMPROVING THE RESISTIVITY OF THE SOURCE/DRAIN AND POLYGATE BETTERS AND IMPROVING THE SEMICONDUCTOR YIELD

SILICIDE FORMING METHOD OF MOSFET OF A SEMICONDUCTOR DEVICE CAPABLE OF IMPROVING THE RESISTIVITY OF THE SOURCE/DRAIN AND POLYGATE BETTERS AND IMPROVING THE SEMICONDUCTOR YIELD

机译:能够提高源/漏和多晶硅氧化物的电阻率并提高半成品率的半导体器件的MOSFET的硅化物形成方法

摘要

PURPOSE: A silicide forming method of MOS FET of a semiconductor device is provided to minimize the change of a channel line width and junction leakage by forming a RTA process of the set temperature as silicide and the titanium/cobalt into multilayer in poly-gate and source/drain top.;CONSTITUTION: A poly-gate(104) is formed at the upper part of a silicon substrate(101) in which the active area and STI(102) are formed. A spacer wall(106) is formed in both side wall of the poly-gate. A hard doping ion injection process is enforced and the source/drain is formed by using the spacer wall and poly-gate as the ion implantation mask. A silicide blocking material is formed in the upper silicon substrate front side in which poly-gate and spacer wall are formed. A multi silicide material is formed in the upper silicon substrate front side in which the silicide blocking pattern(108a) is formed.;COPYRIGHT KIPO 2010
机译:用途:提供一种半导体器件的MOS FET硅化物形成方法,以通过将设定温度作为硅化物和钛/钴的RTA工艺形成在多晶硅栅中的多层结构,从而最大程度地减小沟道线宽的变化和结泄漏。组成:在形成有有源区和STI(102)的硅衬底(101)的上部形成多晶硅栅(104)。在多晶硅栅的两个侧壁中形成有间隔壁(106)。通过使用隔离壁和多晶硅栅作为离子注入掩模,可以实施硬掺杂离子注入工艺,并形成源/漏。硅化物阻挡材料形成在其中形成有多晶硅栅和间隔壁的上硅基板正面。在形成硅化物阻挡图案(108a)的上硅衬底正面中形成多层硅化物材料。; COPYRIGHT KIPO 2010

著录项

  • 公开/公告号KR20100079191A

    专利类型

  • 公开/公告日2010-07-08

    原文格式PDF

  • 申请/专利权人 DONGBU HITEK CO. LTD.;

    申请/专利号KR20080137607

  • 发明设计人 PARK DONG HO;

    申请日2008-12-30

  • 分类号H01L21/24;H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 18:32:18

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