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SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, SCANNING TEST PATTERN GENERATION METHOD, AND ITS PROGRAM

机译:半导体集成电路,半导体集成电路设计方法,扫描测试图案生成方法及其程序

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, a semiconductor integrated circuit design method, a scanning test pattern generation method, and a program capable of reducing cost in a scanning test.;SOLUTION: The semiconductor integrated circuit 1 includes a controlling scanning test component circuit which a test value is scanned therein and outputs the test value to a combination circuit 203 and an observing scanning test component circuit which the test value scanned in the controlling scanning test component circuit is scanned therein in parallel and an output value output by the combination circuit 203 based on a test value from the controlling scanning test component circuit is input thereto to scan out the output value.;COPYRIGHT: (C)2011,JPO&INPIT
机译:解决的问题:提供一种半导体集成电路,一种半导体集成电路设计方法,一种扫描测试图案生成方法以及一种能够降低扫描测试成本的程序。解决方案:半导体集成电路1包括控制扫描在其中扫描测试值并且将该测试值输出到组合电路203的测试部件电路和观察扫描测试部件电路,在其中并行扫描在控制扫描测试部件电路中扫描的测试值,并且通过输入来自控制扫描测试组件电路的测试值的组合电路203以扫描输出值。COPYRIGHT:(C)2011,JPO&INPIT

著录项

  • 公开/公告号JP2011094986A

    专利类型

  • 公开/公告日2011-05-12

    原文格式PDF

  • 申请/专利权人 RENESAS ELECTRONICS CORP;

    申请/专利号JP20090246379

  • 发明设计人 OKUMURA KAZUO;

    申请日2009-10-27

  • 分类号G01R31/28;H01L21/822;H01L27/04;

  • 国家 JP

  • 入库时间 2022-08-21 18:24:53

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