PATTERN ARRANGEMENT METHOD, SILICON WAFER AND SEMICONDUCTOR DEVICE

摘要

A pattern arrangement method including using a stepper to arrange a plurality of chip patterns arranged parallel to a first direction and a second direction on a silicon wafer using a reticule which includes a plurality of patterns expanded in the first direction and the second direction which intersects the first direction and arranged linearly and intermittently, wherein the stepper adjusts the position of the reticule and the silicon wafer which faces the reticule so that an axis in which a cleavage plane of the silicon wafer and a surface arranged with the pattern on the silicon wafer intersect, and the first direction are different.