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Methods for fabricating semiconductor devices having reduced gate-drain capacitance
Methods for fabricating semiconductor devices having reduced gate-drain capacitance
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机译:具有减小的栅极-漏极电容的半导体器件的制造方法
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摘要
Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench.
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