A method is provided for manufacturing an integrated circuit including a short channel (SC) device (16) and a long channel (LC) device (18) each overlaid by an interlayer dielectric (75). The SC device (16) has an SC gate stack (34), and the LC device (18) initially has a dummy gate (50). In one embodiment, the method includes the steps of removing the dummy gate (50) to form an LC device trench (96) and depositing metal gate material (98) over the SC device (16) and the LC device (18). The metal gate material (98) contacts the SC gate stack (34) and substantially fills the LC device trench (96).
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