首页> 外国专利> Complementary Metal-Oxide SemiconductorCMOS Field-Effect Transistor Having Dual Work Function Gate And Method of Manufacturing The Same

Complementary Metal-Oxide SemiconductorCMOS Field-Effect Transistor Having Dual Work Function Gate And Method of Manufacturing The Same

机译:具有双功函数门的互补金属氧化物半导体CMOS场效应晶体管及其制造方法

摘要

PURPOSE: A CMOS transistor with a dual work function gate and a method for manufacturing the same are provided to reduce at least two steps of a lithography process by forming an NMOS transistor and a PMOS transistor gate symmetrically by spacer etching method. CONSTITUTION: A semiconductor substrate(100) is divided into a first area(140a) and a second area(150a). An NMOS transistor is formed in the first area. A PMOS transistor is formed in the second area. The NMOS transistor includes a first gate pattern(125), a second gate pattern(135), a source/drain area of n-type and an NMOS gate. The first gate pattern and the second gate pattern are in the form of spacer shapes. The source/drain region of n-type is formed in the both side of the NMOS gate of the semiconductor substrate. The PMOS transistor includes a PMOS gate and a source/drain region of p-type formed in the both side of the PMOS gate of the semiconductor substrate.
机译:目的:提供具有双功函数栅极的CMOS晶体管及其制造方法,以通过间隔物蚀刻法对称地形成NMOS晶体管和PMOS晶体管栅极来减少光刻工艺的至少两个步骤。构成:半导体衬底(100)被分为第一区域(140a)和第二区域(150a)。在第一区域中形成NMOS晶体管。在第二区域中形成PMOS晶体管。 NMOS晶体管包括第一栅极图案(125),第二栅极图案(135),n型的源极/漏极区域和NMOS栅极。第一栅极图案和第二栅极图案为间隔物形状的形式。在半导体衬底的NMOS栅极的两侧形成n型的源极/漏极区域。 PMOS晶体管包括PMOS栅极和在半导体衬底的PMOS栅极的两侧形成的p型源/漏区。

著录项

  • 公开/公告号KR101027769B1

    专利类型

  • 公开/公告日2011-04-07

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20080078102

  • 发明设计人 나기열;최문호;김영석;

    申请日2008-08-08

  • 分类号H01L21/336;H01L29/78;

  • 国家 KR

  • 入库时间 2022-08-21 17:50:23

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