首页> 外国专利> VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND DIODES HAVING GRADED DOPED REGIONS AND METHODS OF MAKING

VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND DIODES HAVING GRADED DOPED REGIONS AND METHODS OF MAKING

机译:具有梯度掺杂区域的垂直结场效应晶体管和二极管及其制造方法

摘要

Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
机译:描述了半导体器件及其制造方法。这些器件可以是结型场效应晶体管(JFET)或二极管,例如结型势垒肖特基(JBS)二极管或PiN二极管。所述器件具有通过外延生长形成的渐变的p型半导体层和/或区域。该方法不需要离子注入。该器件可以由宽带隙半导体材料(例如碳化硅(SiC))制成,并且可以用于高温和高功率应用中。

著录项

  • 公开/公告号KR20120031071A

    专利类型

  • 公开/公告日2012-03-29

    原文格式PDF

  • 申请/专利权人 SS SC IP LLC;

    申请/专利号KR20127001267

  • 发明设计人 CHENG LIN;MAZZOLA MICHAEL;

    申请日2010-06-18

  • 分类号H01L29/808;H01L29/861;H01L21/337;

  • 国家 KR

  • 入库时间 2022-08-21 17:10:19

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