Hardware driven processor state storage prior to entering a low power mode

摘要

An interrupt controller for managing interrupt requests comprises interrupt control circuitry in a first domain, the first domain being switchable to a low-power mode, and interrupt request monitoring circuitry in a second domain. The interrupt control circuitry is responsive to a low power request signal received by the interrupt controller to communicate interrupt select information to the interrupt request monitoring circuitry prior to the first domain being switched to a low power mode, the interrupt select information identifying interrupt requests which indicate exit from the low power mode. The interrupt request monitoring circuitry comprises a select information store configured to store the select information communicated to the interrupt request monitoring circuitry by the interrupt control circuitry. The interrupt request monitoring circuitry comprises interrupt inputs for receiving the interrupt requests, and is responsive to a received interrupt request identified by the stored interrupt select information as indicating exit from the low power mode to trigger switching of the first domain out of the low power mode.