Method for manufacturing e.g. p-channel FET, for CPU, involves forming gate electrode structure above crystalline threshold voltage-adjusting layers, and forming drain and source regions of transistor in active region of transistor

摘要

The method involves forming crystalline threshold voltage-adjusting layers on a semiconductor base material. A silicon layer is formed on the crystalline threshold voltage-adjusting layers. A gate electrode structure (260A) is formed above the crystalline threshold voltage-adjusting layers by forming a gate dielectric layer (261) and another gate dielectric layer on the former gate dielectric layer (262A). Drain and source regions of p-channel transistor (250A) are formed in an active region (202A) of the p-channel transistor. The crystalline threshold voltage-adjusting layers are formed by performing a chemical vapor deposition (CVD) epitaxial process at low pressure for separating silicon/germanium containing material and controlling germanium concentration in separation atmosphere of the CVD epitaxial process. The crystalline threshold voltage-adjusting layers comprise silicon/germanium alloy. An independent claim is also included for a FET.