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Semiconductor memory device having dummy conductive patterns on interconnection
Semiconductor memory device having dummy conductive patterns on interconnection
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机译:在互连上具有伪导电图案的半导体存储器件
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摘要
A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.
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