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Low temperature implant scheme to improve BJT current gain
Low temperature implant scheme to improve BJT current gain
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机译:低温注入方案可提高BJT电流增益
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摘要
A process of forming an integrated circuit containing an npn BJT and an NMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting n-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the NMOS transistor. A process of forming an integrated circuit containing a pnp BJT and a PMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting p-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the PMOS transistor. A process of forming an integrated circuit containing an implant region by cooling the integrated circuit substrate to 5° C. or colder and implanting atoms, at a specified minimum dose according to species, into the implant region.
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