antifuse with the use of non-planar topology

摘要

Herein, techniques for providing non-volatile antifuse-memory elements and other antifuse connectors discloses. In some embodiments, the antifuse-memory elements with non-planar topology, such as, for example, configured finfet topology. In some such embodiments, the manipulated and fin-topology be used in order to effectively transistors with a lower breakdown voltage, when points with improved emission is to be generated, for use in non-volatile antifuse-memory elements with lower voltage, are suitable. In an exemplary embodiment, a semiconductor anti-fuse device is provided, which is a non-planar diffusion region, with a fin with a tapering section is configured, a dielectric insulation layer on the fin, which contains the tapering section, and a gate material on the dielectric insulation layer contains. The conical portion of the fin can be, for example, by oxidation, etching and / or ablation and can be provided in some cases, it contains a base region, and a dilute region and the dilute region is at least 50% thinner than the base region.