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DECODING METHOD, DECODING CIRCUIT, MEMORY STORAGE DEVICE AND CONTROLLING CIRCUIT UNIT

机译:解码方法,解码电路,存储装置和控制电路单元

摘要

A decoding method, a memory storage device, a memory controlling circuit unit and a decoding circuit for low density parity code (LDPC) are provided. The decoding method includes: reading a data bit of each memory cell; performing a parity check procedure on the data bits to generate a plurality of checks; in an iterative decoding of LDPC, obtaining a reliability message of each data bit according to the checks and deciding an index of an error bit from the data bits according to the reliability messages; determining whether the index of the error bit and the checks comply with a parity criteria; and if the index of the error bit and the checks comply with the parity criteria, stopping the iterative decoding and outputting the index of the error bit. Accordingly, a decoding latency is decreased.
机译:提供了一种用于低密度奇偶校验码(LDPC)的解码方法,存储器存储设备,存储器控制电路单元和解码电路。该解码方法包括:读取每个存储单元的数据位;以及读取每个存储单元的数据位。对数据位执行奇偶校验过程,以产生多个校验;在LDPC的迭代解码中,根据所述校验获得每个数据比特的可靠性消息,并根据所述可靠性消息从所述数据比特中确定错误比特的索引;确定错误位的索引和校验是否符合奇偶校验标准;如果错误位的索引和校验符合奇偶校验标准,则停止迭代解码并输出错误位的索引。因此,减少了解码等待时间。

著录项

  • 公开/公告号US2015113353A1

    专利类型

  • 公开/公告日2015-04-23

    原文格式PDF

  • 申请/专利权人 PHISON ELECTRONICS CORP.;

    申请/专利号US201414145989

  • 发明设计人 CHIEN-FU TSENG;

    申请日2014-01-01

  • 分类号H03M13/11;G06F11/10;

  • 国家 US

  • 入库时间 2022-08-21 15:23:57

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