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Decoding method, memory controlling circuit unit, and memory storage device

机译:解码方法,存储器控制电路单元和存储器存储设备

摘要

The present invention provides a decoding method, a memory controlling circuit unit, and a memory storage device. The decoding method includes: receiving a plurality of commands; reading a first physical programming unit to obtain a plurality of first data respectively by using a plurality of first reading voltage groups of a plurality of reading voltage groups based on a first read command of the plurality of commands and executing a first decoding operation in each of the plurality of first data, wherein a number of the plurality of first reading voltage groups is less than a number of the plurality of reading voltage groups; and executing other commands being different from the first read command of the plurality of commands when unsuccessfully executing the first decoding operation for each of the plurality of first data.
机译:本发明提供了一种解码方法,存储器控制电路单元和存储器存储设备。 解码方法包括:接收多个命令; 读取第一物理编程单元以通过基于多个命令的第一读取命令使用多个读取电压组的多个第一读取电压组来获得多个第一数据,并在每个命令中执行第一解码操作 多个第一数据,其中多个第一读取电压组的多个小于多个读取电压组的数量; 当对多个第一数据中的每一个执行第一解码操作时,执行与多个命令的第一个命令不同的命令。

著录项

  • 公开/公告号US11145372B2

    专利类型

  • 公开/公告日2021-10-12

    原文格式PDF

  • 申请/专利权人 PHISON ELECTRONICS CORP.;

    申请/专利号US201916285178

  • 发明设计人 MING-JEN LIANG;

    申请日2019-02-25

  • 分类号G11C16/08;G06F3/06;G11C16/26;G11C16/14;G11C16/24;G11C11/56;G11C16/04;

  • 国家 US

  • 入库时间 2024-06-14 22:12:31

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