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Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic
Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic
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机译:使用热氧化物选择栅极电介质作为选择栅极并使用局部替换栅极作为逻辑的集成技术
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摘要
A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.
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