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Enhancing integrity of a high-K gate stack by protecting a liner at the gate bottom during gate head exposure
Enhancing integrity of a high-K gate stack by protecting a liner at the gate bottom during gate head exposure
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机译:通过在栅头暴露期间保护栅底部的衬里来增强高K栅堆叠的完整性
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摘要
Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.
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