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Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage
Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage
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机译:具有低寄生BJT增益和稳定阈值电压的横向绝缘栅双极晶体管结构
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摘要
A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.
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