WAFER LEVEL ENCAPSULATION STRUCTURE, FABRICATION METHODS AND VIABLE ENGINEERED SUBSTRATE CONCEPT

摘要

The present invention concerns a hermetic silicon wafer structure comprising a patterned SOI MEMS wafer, a single crystal Si cap attached to the SOI MEMS wafer,and a hermetic silicon-oxide sealing ring in between the said MEMS wafer and the single crystal Si cap. The invention also concerns a silicon wafer structure comprising a silicon-on-insulator wafer embodying MEMS devices,and a single crystal silicon cap attached to the silicon-on- insulator wafer by means of a silicon-oxide sealing ring such that the single crystal silicon cap, the silicon-oxide sealing ring and the silicon-on-insulator wafer define a hermetic cavity around the MEMS devices. Further, the invention concerns methods of fabricating a wafer and a method of manufacturing a Viable Engineered Substrate comprising a patterned SOI MEMS wafer and a single crystal Si cap.