A method for fabricating an integrated circuit, including various types of gate - stacks in first and second regions

摘要

A method for fabricating an integrated circuit comprising the steps of:The formation of a first plurality of gate - stack - layers (3, 3 '', 5, 7) in a first area (ar) and in a second region (pr) on a substrate (1);The removal of the first plurality of gate - stack - layers (3, 5, 7) of the first area (ar);Forming a second plurality of gate - stack - layers (30, 31, 32, 33) in the first area (ar) and in the second region (pr) on the substrate (1);Removal of the second plurality of gate - stack - layers (30, 31, 32, 33) of a subregion (cr) of the first area (ar), as a result of which a plurality of cells - gate - stacks (cg1, cg2) from the second plurality of gate - stack - layers (30, 31, 32, 33) is obtained;Removal of the second plurality of gate - stack - layers (30, 31, 32, 33) of the second region (pr), so that the first plurality of gate - stack - layers (3, 5, 7) is exposed; forming a side wall - liner (13) on the side walls of the plurality of cells - gate - stacks (cg1, cg2);The formation of a third plurality of gate - stack - layers (30 '', 11), the at least partially on the side wall - liner (13) are adjacent in the subregion (cr);The formation of a plurality of second gate - stacks (cg1, cg2) in the subregion (cr) by structuring the third plurality of gate - stack - layers (30 '', 11), wherein the step of patterning of the third plurality of gate - stack - layers (30'', 11) of the side wall - liner (13) is removed.