Self-stabilization techniques for intermediate power level in stacked-Vdd integrated circuits using DC-balanced coding methods

摘要

Two new parallel bus coding methods for generating a DC-balanced code with additional bits are proposed to achieve the self-stabilization of the intermediate power level in Stacked-Vdd integrated circuits. They contribute to producing a uniform switching current in parallel inputs and outputs (I/Os). Type I coding minimizes the difference in the number of switchings between the upper and lower CMOS I/Os by 8B/10B coding followed by toggle conversion. Type II coding, in which the multi-value running disparity control feature is integrated into the bus-invert coding, requires only one redundant bit for any wider bus. Their DC-balanced feature and the stability effect of the intermediate power level in the Stacked-Vdd structure were experimentally confirmed from the measurement results obtained from the developed test chips. (C) 2016 The Japan Society of Applied Physics