On-Chip Low-Power Circuit Techniques for Power Management Regulators in Mixed-Signal Integrated Circuits.

摘要

Integration of different circuits in a single chip is an unstoppable trend as the technologyis being pushed forward. This enables more sophisticated functions to be embedded in a farsmaller physical area. Power management circuits will definitely take an important part in thisdesign revolution because a more demanding supply voltage quality is required by differentsignal blocks.;In this thesis, a converter and two different regulators with the emphasis on speed, power,noise interferences and silicon area will be discussed to accommodate the requirements fordifferent points of load.;An output voltage ripple aware design for different voltage ramp signal of voltage-modeCCM random frequency buck converter for conductive EMI reduction is proposed to illustratethe effects of pulse-width-modulation ramp signal on the output voltage ripple. A mathematical analysis has been carried out to model the output voltage ripple of a randomswitching frequency buck converter. Simulations of the converter have been undertaken andmeasured results from the converter, fabricated with a standard 0.35mum CMOS process, verifythe proposed design approach. From experimental results, a carefully designed ramp canreduce the output voltage ripple by more than 8 times without significant influence on the inductor current spectrum spread and any increment on the output filtering inductance andcapacitance compared to the conventional design.;An output capacitor-less low-dropout regulator for on chip application with activefeedback and slew-rate enhancement circuit is presented. The feedback compensation schemeand transient response enhancement circuit have been modeled and experimentally verified ina standard 0.35mum CMOS process. The total compensation capacitance is limited to 7pF.From experimental results, the implemented regulator can operate from a supply voltage of 1.8V to 4.5V with a minimum dropout voltage of 0.2V at maximum 100mA load and totalquiescent current of 20muA.;A wide loading range output capacitor-less low-dropout regulator with a Power SupplyRejection (PSR) boosting filter circuit for improving supply noise rejection at middle to highfrequency is proposed. A model and experimental verification have been completed with astandard 0.13?m CMOS process. 1pF on-chip capacitance is delegated to stabilitycompensation and 20pF capacitance is used for the PSR filter. From experimental results, theimplemented regulator can operate with a supply voltage of 1.2V with a nominal dropoutvoltage of 0.2V at maximum 50mA load and total quiescent current of 37.32muA with 40dBpower supply rejection at 1MHz across entire loading range.