This nacelle (1) of silicon wafer packaging comprises at least one location (7) for receiving the wafer, delimited by four notches (5A-5C) located along a geometric contour (C) and each having a bottom wall (53). At least a portion of the bottom wall (53) of each notch (5A-5C) is non-parallel with at least one portion (53) of the two adjacent notches along the contour (C) and the nacelle (1) has a aperture (42) for passage of the wafer, parallel to the location (7).
展开▼