STACKED CHIPSET HAVING INSULATING LAYER AND SECONDARY LAYER AND METHOD OF FORMING THE SAME

摘要

PROBLEM TO BE SOLVED: To solve nonlinearity and power handling issues for RF switches and power amplifiers resulting from nonlinear parasitic capacitances produced at an interface between high-resistivity Si and buried SiOin an SOI substrate at RF frequencies in a multi-band and/or multi-mode RF chipset.SOLUTION: A chipset includes a sheet of glass, quartz or sapphire, and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also disclosed is a method of forming a chipset.SELECTED DRAWING: Figure 1