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Gate with self-aligning ledge of enhancement mode GaN transistor

机译:具有增强型GaN晶体管自对准凸耳的栅极

摘要

An enhancement mode GaN transistor having a small gate leakage current between a gate contact and a 2DEG region, and a method of producing the same. The enhancement mode GaN transistor has a GaN layer and a barrier layer disposed on the GaN layer, wherein a 2DEG region is formed between the GaN layer and the barrier layer, and a source contact and a drain contact are arranged on the barrier layer Has been done. The GaN transistor further includes a P-type gate material formed on the barrier layer and between the source contact and the drain contact, and a gate metal disposed on the P-type gate material, the P-type material being in contact with the source contact And a set of self-aligned ledges extending toward the drain contact.
机译:在栅极接触和2DEG区域之间具有小的栅极泄漏电流的增强型GaN晶体管及其制造方法。增强型GaN晶体管具有GaN层和设置在GaN层上的势垒层,其中在GaN层和势垒层之间形成2DEG区域,并且在势垒层上布置有源极触点和漏极触点。完成。 GaN晶体管还包括:形成在势垒层上并且在源极接触与漏极接触之间的P型栅极材料;以及设置在P型栅极材料上的栅极金属,该P型材料与源极接触。触头和一组朝排水触头延伸的自对准壁架。

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