METHODS AND STRUCTURES FOR SPLIT GATE MEMORY CELL SCALING WITH MERGED CONTROL GATES

摘要

A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.