首页>
外国专利>
Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device
Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device
展开▼
机译:在电绝缘隔离的鳍式场效应晶体管(FinFET)器件中形成嵌入式源极和漏极区域以防止底部泄漏
展开▼
页面导航
摘要
著录项
相似文献
摘要
Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (finFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. The device further includes a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions may be doped and the epi bottom region undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).
展开▼