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Reducing source contact to gate spacing to decrease transistor pitch
Reducing source contact to gate spacing to decrease transistor pitch
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机译:减少源极与栅极间距的接触以减小晶体管间距
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摘要
Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in the active area; forming source and drain contacts over the source and drain regions, where a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor; and using one or more modified masks for forming doping profiles for the source region and the drain region.
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