A NOVEL HIGH SPEED PULSE SWALLOW BASED FRACTIONAL-N FREQUENCY DIVIDER CIRCUIT

摘要

A fractional-N frequency dividing system comprisingdual modulus prescaler for counting upto two alterable counting state, pulse and swallow counter to count bits corresponding to division ratio and logical operator based devices operatively connected with the swallow counter.The said prescaler and the swallow counterare operatively connected to a D-FF device enabling changing the counting state of the prescaler depending on the counting state of the swallow counter and the logical operator selectively disabledclock input of the swallow counter based on the counting state of the swallow counter for facilitating offset free division. In addition the proposed design can eliminate the presence of frequency dependent delay unit at the output of the pulse counter. To synchronize the pulse and swallow counter, preset enable signal has been generated without any frequency dependent RC network. Also, there is no need of any special design for the swallow counter as it is the reduced bit version of the program counter. Speed of the swallow counter has been greatly improved as well as offset division of any conventional pulse swallow frequency divider problems were eliminated due to the dummy bits model.