PULSE SWALLOW FREQUENCY DIVIDING CIRCUIT

摘要

PURPOSE:To mitigate the restriction in the design of a frequency synthesizer, by controlling the frequency dividing ratio of the 1st counter with the information of the 2nd and 3rd counters and obtaining an arbitrary integer number of frequency dividing ratio. CONSTITUTION:A prestage variable frequency divider 9 is the 1st counter which performs frequency division of a pair of frequency dividing ratios P and P-0.5 in response to the logical level ''1'' or ''0'' of a control signal 200 to an input signal 100, a programmable counter 2 is the 2nd counter which performs frequency division in the frequency dividing ratio of a positive integer B in cascade connection with the 1st counter, and a programmable counter 3 is the 3rd counter which is cascade-connected to the 1st counter and can count a positive integer A equal to or smaller than the B. When the counter counts B-set of outputs of the frequency divider 9, an output pulse is generated, the couners 2, 3 are reset, the next count is started, the signal 200 is changed from ''1'' to ''0'' and the frequency divider 9 is controlled for the frequency division by the frequency dividing ratio (P-0.5).