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首页> 外文期刊>Microelectronics journal >A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in Delta Sigma fractional-N PLL frequency synthesizer
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A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in Delta Sigma fractional-N PLL frequency synthesizer

机译:利用Delta Sigma分数N分频PLL频率合成器中提出的PFD和脉冲吞咽分频器电路实现快速高效的恒定环路带宽

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This work presents the design of a Delta Sigma fractional-N PLL frequency synthesizer with a new loop bandwidth calibration and automatic frequency control (AFC) circuit, applicable for wide band RF communication system. This new and unique loop bandwidth calibration circuit has been implemented using logarithmic and antilogarithmic (Base2) architecture. This architecture is an efficient design technique as well as faster operation in CMOS domain. The operating frequency range of the Delta Sigma fractional-N PLL frequency synthesizer is from 2.158 to 5.133 GHz. The variation of LC VCO gain (K-vco) is obvious due to wide band application and it varies from 30.65 MHz/Volt to 368 MHz/Volt for the frequency range of 2.158-5.133 GHz. Constant loop bandwidth is maintained by controlling the charge pump current. Power consumption of the Delta Sigma fractional-N PLL frequency synthesizer is 34 mW from a 1.2 Volt power supply and the work has been carried out in 0.13 mu m standard CMOS process. Also, this design includes an automatic frequency control unit for the LC VCO circuit which is coarsely tuned within 1.825 mu s for K-VFC=10 for worst case condition and it completes the loop bandWidth (LBW) calibration within 7.84 mu s for K-LBC=150 for worst case condition. The maximum locking time of the AZ fractional-N PLL frequency synthesizer with loop bandwidth calibration and automatic frequency control circuit is 12.7 mu s for Km = 10 and K-LBC = 150 for worst case condition. The AZ fractional-N PLL is locked much faster than any work reported earlier using the proposed PFD, CP, proposed pulse swallow divider, efficient AFC circuit for LC VCO and a new loop BW calibration technique in transistor level simulation using Cadence SpectreRF. The main advantage of this loop bandwidth calibration technique is that the calibration time can be adjusted according to the PLL output frequency, loop bandwidth calibration accuracy and tuning frequency range of the LC VCO.
机译:这项工作提出了具有新环路带宽校准和自动频率控制(AFC)电路的Delta Sigma分数N分频PLL频率合成器的设计,适用于宽带RF通信系统。这种新的,独特的环路带宽校准电路已经使用对数和反对数(Base2)架构实现。这种架构是一种有效的设计技术,并且在CMOS域中的运行速度更快。 Delta Sigma分数N PLL频率合成器的工作频率范围是2.158至5.133 GHz。由于宽带应用,LC VCO增益(K-vco)的变化很明显,在2.158-5.133 GHz的频率范围内,其变化范围为30.65 MHz /伏至368 MHz /伏。通过控制电荷泵电流可保持恒定的环路带宽。 Delta Sigma分数N PLL频率合成器的功耗为1.2伏电源,功耗为34 mW,工作已在0.13μm的标准CMOS工艺中进行。此外,该设计还包括用于LC VCO电路的自动频率控制单元,对于最坏的情况,该自动频率控制单元在K-VFC = 10的情况下可在1.825μs内进行粗调,并在K-VFC = 7.84 s内完成环路带宽(LBW)的校准。对于最坏情况,LBC = 150。带有环路带宽校准和自动频率控制电路的AZ小数N分频PLL频率合成器的最大锁定时间在Km = 10时为12.7μs,在最坏情况下为K-LBC = 150。使用拟议的PFD,CP,拟议的脉冲吞咽分频器,用于LC VCO的高效AFC电路以及采用Cadence SpectreRF进行晶体管级仿真的新环路带宽校准技术,AZ小数N PLL的锁定速度比先前报告的任何工作快得多。这种环路带宽校准技术的主要优点是可以根据PLL输出频率,环路带宽校准精度和LC VCO的调谐频率范围来调整校准时间。

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