首页> 外国专利> 3D LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS

3D LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS

机译:通过3D集成电路的基板背带实现3D闩锁抑制和基板噪声耦合降低

摘要

When an overview of integrated circuit devices, the one end portion to the upper surface completely through the substrate, the substrate and the other end has a conductor extending in the rear substrate. In various embodiments, the conductors are isolated from all of the conductors and the device features on the chip adjacent to the bottom of any of the RDL all conductors and / or the 3D integrated circuit structure is isolated from the substrate rear surface side. There is also described the manufacturing method.
机译:当对集成电路器件进行概述时,其一端部至上表面完全穿过基板,基板的另一端具有在后基板中延伸的导体。在各个实施例中,导体与所有导体隔离,并且芯片上的器件特征与任何RDL的底部相邻,所有导体和/或3D集成电路结构与衬底背面侧隔离。还描述了制造方法。

著录项

  • 公开/公告号KR101651047B1

    专利类型

  • 公开/公告日2016-08-24

    原文格式PDF

  • 申请/专利权人 시놉시스 인크.;

    申请/专利号KR20157007660

  • 发明设计人 카와 자밀;모로즈 빅터;

    申请日2013-08-29

  • 分类号H01L23/48;H01L21/768;H01L23/00;

  • 国家 KR

  • 入库时间 2022-08-21 14:12:02

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