首页> 外国专利> Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits

Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits

机译:通过用于3D集成电路的基板回拉装置来抑制闩锁并降低基板噪声耦合

摘要

Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.
机译:粗略地描述,一种集成电路器件具有导体,该导体完全延伸穿过基板,一端连接到基板顶侧表面,而另一端连接到基板后侧表面。在各种实施例中,导体与衬底背面上的所有RDL导体绝缘,和/或与3D集成电路结构中的任何下相邻芯片上的所有导体和器件特征绝缘。还描述了制造方法。

著录项

  • 公开/公告号US9190346B2

    专利类型

  • 公开/公告日2015-11-17

    原文格式PDF

  • 申请/专利权人 VICTOR MOROZ;JAMIL KAWA;

    申请/专利号US201213601394

  • 发明设计人 JAMIL KAWA;VICTOR MOROZ;

    申请日2012-08-31

  • 分类号G06F17/50;H01L23/48;H01L21/768;H01L23/00;

  • 国家 US

  • 入库时间 2022-08-21 14:30:21

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