Heterogeneous integration of 3D Si and III-V vertical nanowire structures for mixed signal circuits fabrication

摘要

A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or Si_xGe_1-x substrate; forming a conformal SiN, SiO_xC_yN_z layer over side and bottom surfaces of the first trenches; filling the first trenches with SiO_x; forming a first mask over portions of the Si, Ge, III-V, or Si_xGe_1-x substrate; removing exposed portions of the Si, Ge, III-V, or Si_xGe_1-x substrate, forming second trenches; forming III-V, III-V_xM_y, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V_xM_y, or Si nanowires and intervening first trenches; removing the SiO_x layer, forming third trenches; and removing the second mask.