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INSPECTION SYSTEM, WAFER MAP DISPLAY DEVICE, WAFER MAP DISPLAY METHOD, AND COMPUTER PROGRAM

机译:检查系统,晶片地图显示装置,晶片地图显示方法和计算机程序

摘要

PROBLEM TO BE SOLVED: To provide a technology by which a failure analysis of a tester can be performed in a short time, and a failure prediction can be also performed.SOLUTION: An inspection system 100 includes a prober 200 and a tester 300. The tester 300 includes a plurality of tester module boards 33 on each of which a plurality of LSIs respectively corresponding to a plurality of DUTs are mounted, a display unit 44 that displays a wafer map indicating inspection results of the plurality of DUTs and/or self-diagnosis results of the tester 300, and a tester control unit 35 including a wafer map drawing application 60 for drawing the wafer map to be displayed on the display unit 44, and the wafer map drawing application 60 displays the inspection result and/or the self-diagnosis result on each of the plurality of DUTs in stages, and the plurality of DUTs on the wafer map is associated with the plurality of LSIs mounted on the plurality of tester module boards 33.SELECTED DRAWING: Figure 1
机译:要解决的问题:提供一种可以在短时间内对测试仪进行故障分析并进行故障预测的技术。解决方案:检查系统100包括探测仪200和测试仪300。测试仪300包括:多个测试仪模块板33,其上分别安装有分别与多个DUT相对应的多个LSI;显示单元44,其显示指示多个DUT的检查结果的晶片图和/或自检。测试仪300的诊断结果,测试仪控制单元35包括用于绘制要显示在显示单元44上的晶片图的晶片图绘制应用程序60,晶片图绘制应用程序60显示检查结果和/或自身多个DUT的每个阶段的诊断结果,并且晶片图上的多个DUT与安装在多个测试器模块板33上的多个LSI相关联。重新1

著录项

  • 公开/公告号JP2018170418A

    专利类型

  • 公开/公告日2018-11-01

    原文格式PDF

  • 申请/专利权人 TOKYO ELECTRON LTD;

    申请/专利号JP2017067047

  • 发明设计人 UCHIDA SHIN;KAGAMI TETSUYA;

    申请日2017-03-30

  • 分类号H01L21/66;G01R31/26;G01R31/28;

  • 国家 JP

  • 入库时间 2022-08-21 13:13:39

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