P-type diamond gate-GaN heterojunction FET structure

摘要

A FET device includes a substrate having top and bottom surfaces, a channel layer on the top surface of the substrate; the channel layer having top and bottom surfaces, at least two recesses extending into the channel layer from the top surface of the channel layer and forming a channel region between the at least two recesses, a gate electrode disposed in each of the at least two recesses, and a drain region and a source region formed in the channel layer on opposite sides of said channel region.