首页> 外国专利> III-V SEMICONDUCTOR STRUCTURE COMPRISING AN ACTIVE SEMICONDUCTOR LAYER OF THE III-V TYPE ON A BUFFER LAYER STACK AND METHOD FOR PRODUCING SEMICONDUCTOR STRUCTURE

III-V SEMICONDUCTOR STRUCTURE COMPRISING AN ACTIVE SEMICONDUCTOR LAYER OF THE III-V TYPE ON A BUFFER LAYER STACK AND METHOD FOR PRODUCING SEMICONDUCTOR STRUCTURE

机译:包括在缓冲层堆上的III-V型有源半导体层的III-V型半导体结构及其制造方法

摘要

The present invention relates to a semiconductor structure, - a buffer layer stack comprising a plurality of III-V material layers, wherein the buffer layer stack comprises at least one layered substructure, each layered substructure having a first buffer layer and a second buffer layer, Wherein the lower surface of each of the second buffer layers is lower than the upper surface of each of the first buffer layers, Said buffer layer stack having an Al content; - an active semiconductor layer of the III-V type provided on the buffer layer stack And Wherein the surface of each of the relaxed layers is sufficiently roughened to inhibit relaxation of each of the second buffer layers including a Root Mean Square (RMS) roughness greater than 1 nm; And a method of manufacturing the semiconductor structure.
机译:本发明涉及一种半导体结构,-包括多个III-V材料层的缓冲层堆叠,其中所述缓冲层堆叠包括至少一个分层的子结构,每个分层的子结构具有第一缓冲层和第二缓冲层,其中,每个第二缓冲层的下表面均低于每个第一缓冲层的上表面。 -设置在缓冲层堆叠上的III-V型有源半导体层,并且其中每个松弛层的表面被充分粗糙化以抑制包括均方根(RMS)粗糙度更大的每个第二缓冲层的松弛。大于1nm;以及制造半导体结构的方法。

著录项

  • 公开/公告号KR101899742B1

    专利类型

  • 公开/公告日2018-09-17

    原文格式PDF

  • 申请/专利权人 에피간 엔브이;

    申请/专利号KR20177005411

  • 发明设计人 델라윈 요프;데흐로테 스테판;

    申请日2015-07-22

  • 分类号H01L21/02;

  • 国家 KR

  • 入库时间 2022-08-21 12:37:04

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