Asymmetric dual gate fully depleted transistor

摘要

Techniques that facilitate an asymmetric dual gate fully depleted transistor are provided. In one example, a transistor device includes a semiconductor channel structure, a first gate structure and a second gate structure. The first gate structure comprises a first length. The second gate structure comprises a second length that is different than the first length. The first gate structure is disposed on a first surface of the semiconductor channel structure and the second gate structure is disposed on a second surface of the semiconductor channel structure.