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Mechanism for adjusting characteristics of inter-stage circuit to mitigate or reduce DCO pulling effect
Mechanism for adjusting characteristics of inter-stage circuit to mitigate or reduce DCO pulling effect
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机译:调整级间电路特性以减轻或减小DCO拉动效应的机制
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摘要
A method of a control circuit of a communication device comprises: receiving a data signal to generate a phase data signal to a digital phase-locked loop (DPLL); using the DPLL to receive the phase data signal, to dynamically lock a particular clock, and to generate a phase modulation signal based on the phase data signal; and determining or adjusting an equivalent capacitance of an inter-stage circuit which is coupled between the DPLL and a power amplifier and configured for processing the phase modulation signal and generating a processed phase modulation signal to the power amplifier.
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