首页> 外文会议>IEEE International Solid- State Circuits Conference >A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling
【24h】

A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling

机译:具有抖动辅助牵引缓解功能的数字频率合成器,用于同时进行DCO和参考路径耦合

获取原文
获取外文期刊封面目录资料

摘要

Injection pulling on frequency synthesizers has become a critical design challenge for high-performance wireless transceivers, especially in highly integrated multiradio platforms, imposing stringent constraints on system-level frequency planning. For instance, the oscillator of the victim phase-locked loop (PLL) can be disturbed by the power-amplifier (PA) output or other nearby PLLs when their fundamental or harmonic frequency components are close to the victim PLL carrier frequency. Although the aggressor waveform in most cases is known a priori, the coupling path and mechanism (electric or magnetic) is complex and varying over time and operating conditions. Hence, the transfer function of the coupling path cannot be predetermined or reliably compensated with foreground calibration. Therefore, recent works [1-4] have proposed adaptive techniques that track the transfer function in the background. However, they only focus on pulling mitigation of the oscillator, and some incur high overhead, e.g., an additional ADC in the case of an analog PLL. In real operation, the interfering signal can affect not only the oscillator but also the input reference clock [1]. The compensation mechanism is different for two coupling paths, i.e. the oscillator pulling mitigation can worsen perturbation caused by reference path coupling, as noted in [5]. To alleviate those issues, this work proposes a dither-assisted pulling mitigation scheme that orthogonalizes the coupling from both DCO and reference paths and allows simultaneous rejection in the background. Moreover, the technique also aims to mitigate different aggressor waveforms while minimizing the hardware overhead. The prototype is implemented in 65nm CMOS and uses a digital PLL architecture for better technology scalability. Various types of interference are injected to the DCO and reference paths simultaneously, and the measurement shows 12 and 22.5dB spectral improvement for the PA and the oscillator mutual pulling, respectively, which validates the effectiveness of the technique.
机译:注入频率合成器已成为高性能无线收发器的一项关键设计挑战,尤其是在高度集成的多无线电平台中,这对系统级频率规划施加了严格的约束。例如,当受害锁相环(PLL)的基频或谐波频率分量接近受害PLL载波频率时,受功率放大器(PA)输出或其他附近的PLL的干扰。尽管在大多数情况下先验的攻击波形是已知的,但是耦合路径和机制(电的或磁的)是复杂的,并且会随时间和操作条件而变化。因此,耦合路径的传递函数不能被预先确定或不能用前景校准可靠地补偿。因此,最近的工作[1-4]提出了在后台跟踪传递函数的自适应技术。但是,它们仅专注于减轻振荡器的负担,并且会产生较高的开销,例如,在模拟PLL的情况下,会产生额外的ADC。在实际操作中,干扰信号不仅会影响振荡器,还会影响输入参考时钟[1]。补偿机制对于两条耦合路径是不同的,即,振荡器拉动的缓解会加剧由参考路径耦合引起的摄动,如[5]中所述。为了缓解这些问题,这项工作提出了一种抖动辅助的拉动缓解方案,该方案正交化了DCO和参考路径的耦合,并允许在后台同时进行剔除。而且,该技术还旨在减轻不同的干扰波形,同时将硬件开销降至最低。该原型在65nm CMOS中实现,并使用数字PLL架构来实现更好的技术可扩展性。同时将各种类型的干扰注入DCO和参考路径,并且测量结果分别显示了PA和振荡器互拉的频谱改善了12和22.5dB,这证明了该技术的有效性。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号