PLL circuit and phase difference detecting circuit that can reduce phase pull-in time and adjust a skew at a higher precision

摘要

A PLL circuit for comparing with a phase comparator 1a phase between an input signal and one of multiphase pulse signals CK0DIV to CKNDIV used as a channel clock generated by an output of a controlled oscillator 5, and controlling an oscillation of the controlled oscillator 5 according to a phase difference signal, comprises a frequency fixing circuit 9 for outputting an activating signal PCSTART for the control when the input signal is nearly equivalent to a frequency of the channel clock and has entered into a capture range of the phase comparator and a selection circuit 7 for selecting as the channel clock a multiphase pulse signal of a closest phase to a generating point of the input signal after generation of the activating signal, and the selection circuit 7 decides whether the input signal is advanced or delayed with respect to the channel clock after having selected a multiphase pulse signal as the channel clock and generates either an advance signal or delay signal according to the advance/delay of the input signal, for controlling a skew adjusting circuit 8 with the advance signal or delay signal.