Integrated circuit latch for flip-flop circuit, adjusts pull down delay characteristics of NAND gates by reducing effective ON state impedance of respective pull down paths

摘要

The latch includes a pair of NAND gates (411,412). The pull down delay characteristics are adjusted using complementary data signals by reducing effective ON state impedance of respective pull down paths, when the output of corresponding NAND gate is pulled from logic 1 to logic 0 by the pull down paths. Independent claims are also included for the following: (a) Multistage latch circuit; (b) Flip-flop circuit for latching data in response to clock signal; (c) Digital magnitude comparator; (d) Analog voltage comparator