In todays aggressively designed integrated circuits (ICs), there exist a large number of critical or near-critical delay input-to-output paths (i.e. paths which have delays close to the maximum delay). Small perturbations in the manufacturing or operation environment of the above ICs can lead to timing failures. Testing for these timing (delay) failures has become a very challenging task. In general, testing is one of the major cost factors in the development and manufacturing of integrated circuit (IC) systems, accounting for as much as 50% of the total manufacturing expenses.; Along with the process of testing the manufactured chips for delay faults, there is a need for diagnosing the cause of the delay failure down to as small a subset of the electronic circuitry as possible. An efficient diagnosis tool can drastically reduce IC re-design time by providing the designers with a small set of possible delay failures to investigate.; This research investigates the problem of path-delay fault diagnosis in digital integrated circuits (ICs). The goal is to develop diagnosis oriented test methodologies along with automated tools that enable designers to quickly locate the failing parts of the IC. The proposed diagnosis framework provides these capabilities for a wide range of industrial circuit design styles including, but not limited to, combinational circuits and sequential circuits.
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