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Three-dimensional charge trapping NAND cell with discrete charge trapping film
Three-dimensional charge trapping NAND cell with discrete charge trapping film
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机译:具有离散电荷俘获膜的三维电荷俘获NAND单元
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摘要
A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.
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