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Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods
Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods
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机译:使用没有介电层和/或功函数金属层的场栅极以减小栅极布局寄生电阻的集成电路以及相关方法
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摘要
Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods are disclosed. At least a portion of the dielectric layers and/or work function metal layers present in active gate(s) is not present in a field gate(s) of a gate in a circuit cell. The field gate(s) have more conductive gate material than the active gate(s). In this manner, the increased volume of gate material in the field gate(s) reduces gate layout parasitic resistance. The active gate(s) retains the dielectric layers and/or work function metal layers to effectively isolate the gate material from a channel of a FET formed from the circuit cell to provide effective channel control. Reducing gate layout parasitic resistance can reduce current (I) resistance (R) (IR) drop to achieve the desired drive strength in the integrated circuit.
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