INTEGRATED CIRCUITS EMPLOYING VARIED GATE TOPOGRAPHY BETWEEN AN ACTIVE GATE REGION(S) AND A FIELD GATE REGION(S) IN A GATE(S) FOR REDUCED GATE LAYOUT PARASITIC CAPACITANCE, AND RELATED METHODS

摘要

Integrated circuits employing varied gate topography between an active gate region(s) and a field gate region(s) in a gate(s) for reduced gate layout parasitic capacitance, and related methods, are disclosed. In exemplary aspects, the gate topography (e.g., height) of a gate in a circuit cell used to form gates for devices formed therein to form an integrated circuit is varied between an active gate and a field gate(s) of the gate. In this manner, the overall volume of material in the gate can be reduced due to the reduction in volume of the field gate(s) to reduce gate layout parasitic capacitance. Reducing gate layout parasitic capacitance in a circuit cell can reduce the overall parasitic capacitance of an integrated circuit formed from the circuit cell to achieve the desired integrated circuit delay performance.