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IGBT DEVICE AND METHOD FOR PACKAGING WHOLE-WAFER IGBT CHIP

机译:封装全晶片IGBT芯片的IGBT装置和方法

摘要

An IGBT device and a method for packaging a whole-wafer IGBT chip. The IGBT device comprises: an entire wafer IGBT chip (33), the upper surface thereof comprising a central gate connection zone (13) and a plurality of emitter connection zones (15, 25) surrounding the central gate connection zone (13), and the lower surface thereof comprising a collecting zone, wherein the emitter connection zones (15, 25) located on the surface of a failure cellular zone of the chip are thinned; a collector washer (32) which is fixed on the lower surface of the chip (33), and an emitter washer (34) which is fixed on the upper surface of the chip (33); a collector electrode (31) which is electrically contacted with the collector washer (32), and an emitter electrode (36) which is electrically contacted with the emitter washer (34); and a gate leading wire (37) which is connected to the central gate connection zone (13), wherein the gate leading wire (37) is insulated from the emitter washer (34) and the emitter electrode (36). The IGBT device avoids the harmful effect of the failure cellular zone in the whole-wafer chip on the performance of the IGBT device.
机译:IGBT器件和用于封装全晶片IGBT芯片的方法。该IGBT器件包括:整个晶片IGBT芯片(33),其上表面包括中心栅极连接区(13)和围绕中心栅极连接区(13)的多个发射极连接区(15、25),以及其下表面包括收集区,其中位于芯片的失效单元区的表面上的发射极连接区(15、25)变薄。固定在芯片(33)的下表面上的集电极垫圈(32)和固定在芯片(33)的上表面上的发射极垫圈(34);与集电垫圈(32)电接触的集电极(31)和与发射垫圈(34)电接触的发射极(36)。栅极引线(37)连接到中心栅极连接区(13),其中栅极引线(37)与发射极垫圈(34)和发射极(36)绝缘。 IGBT器件避免了整个晶片芯片中的失效单元区对IGBT器件性能的有害影响。

著录项

  • 公开/公告号EP3029734B1

    专利类型

  • 公开/公告日2020-05-06

    原文格式PDF

  • 申请/专利权人 ZHUZHOU CSR TIMES ELECTRIC CO. LTD.;

    申请/专利号EP20140831797

  • 发明设计人 LI JILU;WU YUDONG;PENG YONGDIAN;

    申请日2014-06-16

  • 分类号H01L23/051;H01L29/739;H01L29/08;H01L29/417;H01L29/66;H01L29/06;

  • 国家 EP

  • 入库时间 2022-08-21 11:42:27

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