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Low voltage NPN with low trigger voltage and high snap back voltage for ESD protection
Low voltage NPN with low trigger voltage and high snap back voltage for ESD protection
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机译:具有低触发电压和高骤回电压的低压NPN,用于ESD保护
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摘要
An area-efficient, low voltage ESD protection device (200) is provided for protecting low voltage pins (229, 230) against ESD events by using one or more stacked low voltage NPN bipolar junction transistors, each formed in a p-type material with an N+ collector region (216) and P+ base region (218) formed on opposite sides of an N+ emitter region (217) with separate halo extension regions (220-222) formed around at least the collector and emitter regions to improve the second trigger or breakdown current (It2) and set the snapback voltage (Vsb) and triggering voltage (Vt1) at the desired level.
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