2-stage ESD protection circuit with high holding voltage and low trigger voltage for high voltage applications

摘要

In this paper, 2-stage Electrostatic Discharge (ESD) protection circuit with high holding voltage and low trigger voltage for high voltage applications is proposed. As semiconductor densities have increased, ESD has become a serious problem in semiconductor processes. The proposed circuit is a stacked structure of the unit structure combined by the first ESD protection circuit and the second ESD protection. The simulation results show that the 2-stage proposed circuit has low trigger voltage and high holding voltage for high voltage applications.